The present application is based on Japanese priority application No.2000-210793 filed on Jul. 12, 2001, the entire contents of which are hereby incorporated by reference.
The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having an insulated gate electrode and a fabrication process thereof.
With the progress in the art of device miniaturization, semiconductor devices forming an advanced high-speed LSIs or advanced memory LSIs are now having a gate length approaching the value of 0.1 xcexcm.
In such highly miniaturized, high-speed semiconductor devices, there emerges a problem of signal delay caused by a parasitic capacitance that is formed at the part of the semiconductor device in which a diffusion region formed adjacent to a gate electrode invades into the region right underneath the gate electrode in the form of extension of the diffusion region.
In order to minimize such an overlap of the extension region, there is proposed a MOSFET that uses a T-shaped gate electrode.
FIG. 1 shows the construction of a conventional MOSFET having such a T-shaped gate.
Referring to FIG. 1, the MOSFET is constructed on a p-type Si substrate 41 and includes a T-shaped gate electrode 43 provided on the Si substrate 41 with a gate oxide film 42 interposed between the Si substrate 41 and the gate electrode 43.
At both lateral sides of the T-shaped gate electrode, there are formed n-type extension regions 44 formed by an ion implantation process of an impurity element such as As, wherein the ion implantation process for forming the extension regions 44 is conducted while using the top part of the T-shaped gate electrode 43 as a mask.
After formation of the n-type extension regions 44, sidewall insulation films (not shown) are provided on both lateral sidewalls of the gate electrode 43, and n+-type diffusion regions 45 are formed in the substrate 41 in the region outside the sidewall insulation films by an ion implantation process of an impurity element such as As while using the sidewall insulation films as a mask.
According to the foregoing process, the extension regions 44 are formed initially with an offset from the bottom lateral edge of the gate electrode, due to the fact that the ion implantation for forming the extension regions 44 has been conducted while using the top part of the T-shaped gate electrode 43 as a mask. This offset, however, disappears as the thermal annealing process for activating the introduced As ions is conducted, and the extension part 44 has a tip end generally coincident to the bottom lateral edge of the T-shaped gate electrode 43 in the state of FIG. 1 in which the thermal annealing process has been conducted.
On the other hand, the structure of FIG. 1 has a drawback, due to the use of the T-shaped gate electrode, in that the control of the process is difficult. Particularly, it has been necessary to use a complex process for forming the T-shaped gate electrode.
More specifically, it has been necessary to apply a lateral etching process to a gate electrode patterned according to an ordinary process, with such a condition that the lateral etching process acts preferentially upon the bottom part of the gate electrode with respect to the gate insulation film. However, control of such a lateral etching process is difficult.
Further, there arises a problem in the MOSFET of FIG. 1 in that B introduced into the gate electrode 43 may invade into the channel region of the MOSFET across the gate insulation film 42 at the time of thermal annealing process for activating the impurity elements introduced by the ion implantation process. When such invasion of B occurs in the channel region, the threshold characteristic of the MOSFET is inevitably modified.
One way to avoid this modification of the threshold characteristic of MOSFET would be to reduce the temperature used for the thermal activation process of the impurity element. However, the use of such a low thermal activation temperature results in insufficient activation of the doped impurity elements, and there can occur the formation of depletion region in the gate region adjacent to the gate insulation film as a result of the insufficient activation of the impurity elements.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device having an insulated gate and fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device having a T-shaped insulated gate wherein the problem of penetration of B across a gate insulation film is eliminated.
Another object of the present invention is to provide a simple and reliable process for fabricating a semiconductor device having a T-shaped insulated gate.
Another object of the present invention is to provide a semiconductor device, comprising:
a substrate including a semiconductor layer at least on a top part thereof;
a gate insulation film provided on said semiconductor layer; and
a gate electrode provided on said gate insulation film,
said gate electrode comprising a first polycrystal layer in contact with said gate insulation film, said first polycrystal layer containing at least Si and Ge, and a second polycrystal layer provided on said first polycrystal layer,
said first polycrystal layer having a reduced lateral size as compared with said second polycrystal layer, said first and second polycrystal layers thereby forming a T-shaped gate electrode.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a gate insulation film on a substrate, said substrate including a semiconductor layer at least on a top part thereof;
depositing a first polycrystal layer containing at least Si and Ge on said semiconductor layer;
depositing a second polycrystal layer of Si on said first polycrystal layer;
patterning said first and second polycrystal layers to form a gate electrode defined by a pair of sidewalls; and
applying an oxidation process to said first and second polycrystal layers such that said first and second polycrystal layers undergo oxidation at said both sidewalls.
According to the present invention, the penetration of B into the channel region of the semiconductor device through the gate insulation film is effectively blocked by interposing the SiGe first polycrystal layer between the gate insulation film and the second polycrystal layer. As a result, the semiconductor device provides a stable threshold characteristic. As a result of the use of the T-shaped gate electrode, the problem of penetration of the extension region of the diffusion region into the channel region right underneath the gate electrode is positively eliminated, and the semiconductor device of the present invention provides a high operational speed.
Further, the use of the SiGe first polycrystal layer facilitates formation of the T-shaped electrode due to the accelerated oxidation rate as compared with an ordinary polysilicon layer. More specifically, the desired T-shaped gate electrode is formed easily in a single oxidation step.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.